This invention relates to an information memory device and more particularly an information memory device of the type wherein external memory informations are sequentially and randomly stored in locations designated by addresses and the stored information is randomly and sequentially read out from the locations designated by addresses.
According to a prior art information memory device of this type, memory informations supplied from outside are sequentially stored in locations of a memory cell array designated by external addresses, or memory informations stored in memory cells at locations designated external addresses are read out. An example of such a memory device may be a speech line switch of a digital telephone exchange, that is a time switch in which a speech path memory device having a plurality of memory cells is used to assign, in a predetermined sequence, time divisioned data on an incoming highway to time slots on an outgoing highway.
In the information memory device of this construction, it is usual to independently supply an address adapted to write an information and an address adapted to read out a stored information from an external source of addresses. For example, in the time switch described above, the data of respective time slots supplied from the incoming highway are randomly stored at predetermined locations in a speech path memory device according to addresses of a switch control memory device installed externally, and where the stored information is read out for time slots of the outgoing highway from the speech path memory device. The stored information is sequentially read out from predetermined positions of the speech path memory device in accordance with address which are the count number of an external counter. Usually, the output from the switch control memory device and the counter output are selectively transferred by using two switches so as to alternately perform the write operation and the read operation described above. One example of such construction is disclosed in K. Tawara et al paper entitled "A time division switching network based on time switches", Review of the Electrical Communication Laboratories, Vol. 27, Nos. 9-10, September-October, 1979, Pages 758-772. Accordingly, it is usual to supply the external address to the memory device at an operation period having a predetermined constant time margin.
However, when one tries to shorten the operation period of the device, that is the memory access time, it is impossible to neglect the time margin. For this reason, it is essential to reduce the memory access time caused by the time margin in order to perform a high speed operation.
For example, for effecting telephone exchange between highways each having 1024 channels at a speed of 8M bits/sec. with the time switch, the prior art time switch described above requires an access time of 30 nanoseconds. With such high speed access time, it is impossible to increase the density of the integrated circuits making it difficult to construct such time switch as an LSI.